3D Interconnect Architectures for Heterogeneous Technologies (Record no. 200457402)

MARC details
000 -LEADER
fixed length control field 07097nam a22005535i 4500
003 - CONTROL NUMBER IDENTIFIER
control field TR-AnTOB
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20231108164925.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 220627s2022 sz | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783030982294
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-3-030-98229-4
Source of number or code doi
040 ## - CATALOGING SOURCE
Original cataloging agency TR-AnTOB
Language of cataloging eng
Description conventions rda
Transcribing agency TR-AnTOB
041 ## - LANGUAGE CODE
Language code of text/sound track or separate title İngilizce
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7874.53
072 #7 - SUBJECT CATEGORY CODE
Subject category code TJFC
Source bicssc
Subject category code TEC008010
Source bisacsh
Subject category code TJFC
Source thema
090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN)
Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR) TK7874.53EBK
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Bamberg, Lennart.
Relator term author.
Relator code aut
-- http://id.loc.gov/vocabulary/relators/aut
245 10 - TITLE STATEMENT
Title 3D Interconnect Architectures for Heterogeneous Technologies
Medium [electronic resource] :
Remainder of title Modeling and Optimization /
Statement of responsibility, etc. by Lennart Bamberg, Jan Moritz Joseph, Alberto García-Ortiz, Thilo Pionteck.
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2022.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Cham :
Name of producer, publisher, distributor, manufacturer Springer International Publishing :
-- Imprint: Springer,
Date of production, publication, distribution, manufacture, or copyright notice 2022.
300 ## - PHYSICAL DESCRIPTION
Extent 1 online resource
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term computer
Media type code c
Source rdamedia
338 ## - CARRIER TYPE
Carrier type term online resource
Carrier type code cr
Source rdacarrier
347 ## - DIGITAL FILE CHARACTERISTICS
File type text file
Encoding format PDF
Source rda
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Part I Introduction -- 1 Introduction to 3D Technologies -- 1.1 Motivation for Heterogenous 3D ICs -- 1.2 3D Technologies -- 1.3 TSV Capacitances—A Problem Resistant to Scaling -- 1.4 Conclusion -- 2 Interconnect Architectures for 3D Technologies -- 2.1 Interconnect Architectures -- 2.2 Overview of Interconnect Architectures for 3D ICs -- 2.3 Three-dimensional Networks on chips -- 2.4 Conclusion -- Part II 3D Technology Modeling -- 3 Power and Performance Formulas -- 3.1 High-Level Formula for the Power Consumption -- 3.2 High-Level Formula for the Propagation Delay -- 3.3 Matrix Formulations -- 3.4 Evaluation -- 3.5 Conclusion -- 4 Capacitance Estimation -- 4.1 Existing Capacitance Models -- 4.2 Edge and MOS Effects on the TSV Capacitances -- 4.3 TSV Capacitance Model -- 4.4 Evaluation -- 4.5 Conclusion -- Part III System Modeling -- xiii -- xiv Contents -- 5 Application and Simulation Models -- 5.1 Overview of the Modeling Approach -- 5.2 Application Traffic Model -- 5.3 Simulation Model of 3D NoCs -- 5.4 Simulator Interfaces -- 5.5 Conclusion -- 6 Bit-level Statistics -- 6.1 Existing Approaches to Estimate the Bit-Level Statistics for -- Single Data Streams -- 6.2 Data-Stream Multiplexing -- 6.3 Bit-Level Statistics with Data-Stream Multiplexing -- 6.4 Evaluation -- 6.5 Conclusion -- 7 Ratatoskr Framework -- 7.1 Ratatoskr for Practitioners -- 7.2 Implementation -- 7.3 Evaluation -- 7.4 Case Study: Link Power Estimation and Optimization -- 7.5 Conclusion -- Part IV 3D-Interconnect Optimization -- 8 Low-Power Technique for 3D Interconnects -- 8.1 Fundamental Idea -- 8.2 Power-Optimal TSV assignment -- 8.3 Systematic Net-to-TSV Assignments -- 8.4 Combination with Traditional Low-Power Codes -- 8.5 Evaluation -- 8.6 Conclusion -- 9 Low-Power Technique for High-Performance 3D -- Interconnects. -- 9.1 Edge-Effect-Aware Crosstalk Classification -- 9.2 Existing Approaches and Their Limitations -- 9.3 Proposed Technique -- 9.4 Extension to a Low-Power 3D CAC -- 9.5 Evaluation -- 9.6 Conclusion -- 10 Low-Power Technique for High-Performance 3D -- Interconnects (Misaligned) -- 10.1 Temporal-Misalignment Effect on the Crosstalk -- 10.2 Exploiting Misalignment to Improve the Performance -- 10.3 Effect on the TSV Power Consumption -- Contents xv -- 10.4 Evaluation -- 10.5 Conclusion -- 11 Low-Power Technique for Yield-Enhanced 3D Interconnects -- 11.1 Existing TSV Yield-Enhancement Techniques -- 11.2 Preliminaries—Logical Impact of TSV Faults -- 11.3 Fundamental Idea -- 11.4 Formal Problem Description -- 11.5 TSV Redundancy Schemes -- 11.6 Evaluation -- 11.7 Case Study -- 11.8 Conclusion -- Part V NoC Optimization for Heterogeneous 3D Integration -- 12 Heterogeneous Buffering for 3D NoCs251 -- 12.1 Buffer Distributions and Depths -- 12.2 Routers with Optimized Buffer Distribution -- 12.3 Routers with Optimized Buffer Depths -- 12.4 Evaluation -- 12.5 Discussion -- 12.6 Conclusion -- 13 Heterogeneous Routing for 3D NoCs -- 13.1 Heterogeneity and Routing -- 13.2 Modeling Heterogeneous Technologies -- 13.3 Modeling Communication -- 13.4 Routing Limitations from Heterogeneity -- 13.5 Heterogeneous Routing Algorithms -- 13.6 Heterogeneous Router Architectures -- 13.7 Low-Power Routing in Heterogeneous 3D ICs -- 13.8 Evaluation -- 13.9 Discussion -- 13.10Conclusion -- 14 Heterogeneous Virtualisation for 3D NoCs -- 14.1 Problem Description -- 14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance -- 14.3 Evaluation -- 14.4 Conclusion -- 15 Network Synthesis and SoC Floor Planning -- 15.1 Fundamental Idea -- 15.2 Modelling and Optimization -- 15.3 Mixed-Integer Linear Program -- 15.4 Heuristic Solution -- xvi Contents -- 15.5 Evaluation -- 15.6 Conclusion -- Part VI Finale -- 16 Conclusion -- 16.1 Putting it all together -- 16.2 Impact on Future Work -- A Appendix -- B Pseudo Codes -- C Method to Calculate the Depletion-Region Widths -- D Modeling Logical OR Relations.
520 ## - SUMMARY, ETC.
Summary, etc. This book describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration. Readers learn about the physical implications of using heterogeneous 3D technologies for SoC integration, while also learning to maximize the 3D-technology gains, through a physical-effect-aware architecture design. The book provides a deep theoretical background covering all abstraction-levels needed to research and architect tomorrow’s 3D-integrated circuits, an extensive set of optimization methods (for power, performance, area, and yield), as well as an open-source optimization and simulation framework for fast exploration of novel designs. Addresses modeling and optimization of (heterogenous) 3D interconnect architectures from the physical to system level; Provides several optimization techniques for all key 3D-interconnect metrics; Presents the only open-source NoC simulator for heterogenous 3D SoCs.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronic circuits.
Topical term or geographic name entry element Embedded computer systems.
Topical term or geographic name entry element Microprocessors.
Topical term or geographic name entry element Computer architecture.
Topical term or geographic name entry element Electronic Circuits and Systems.
Topical term or geographic name entry element Embedded Systems.
Topical term or geographic name entry element Processor Architectures.
653 #0 - INDEX TERM--UNCONTROLLED
Uncontrolled term Interconnects (Integrated circuit technology)
Uncontrolled term Systems on a chip
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Joseph, Jan Moritz.
Relator term author.
Relator code aut
-- http://id.loc.gov/vocabulary/relators/aut
Personal name García-Ortiz, Alberto.
Relator term author.
Relator code aut
-- http://id.loc.gov/vocabulary/relators/aut
Personal name Pionteck, Thilo.
Relator term author.
Relator code aut
-- http://id.loc.gov/vocabulary/relators/aut
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="https://doi.org/10.1007/978-3-030-98229-4">https://doi.org/10.1007/978-3-030-98229-4</a>
Materials specified Springer eBooks
Public note Online access link to the resource
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Library of Congress Classification
Koha item type E-Book
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Not for loan Collection code Home library Current library Date acquired Source of acquisition Inventory number Total Checkouts Full call number Barcode Date last seen Copy number Date shelved Koha item type Public note
    Library of Congress Classification Geçerli değil-e-Kitap / Not applicable-e-Book E-Kitap Koleksiyonu Merkez Kütüphane Merkez Kütüphane 11/10/2023 Satın Alma / Purchase ELE   TK7874.53EBK EBK02577 08/11/2023 1 08/11/2023 E-Book
Devinim Yazılım Eğitim Danışmanlık tarafından Koha'nın orjinal sürümü uyarlanarak geliştirilip kurulmuştur.