MARC details
| 000 -LEADER |
|---|
| fixed length control field |
02896nam a22005055i 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
TR-AnTOB |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20231116113529.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
|---|
| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
211031s2022 si | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9789811631993 |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.1007/978-981-16-3199-3 |
| Source of number or code |
doi |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
TR-AnTOB |
| Language of cataloging |
eng |
| Description conventions |
rda |
| Transcribing agency |
TR-AnTOB |
| 041 ## - LANGUAGE CODE |
|---|
| Language code of text/sound track or separate title |
İngilizce |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7868.L6 |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TJFC |
| Source |
bicssc |
|
|---|
| Subject category code |
TEC008010 |
| Source |
bisacsh |
|
|---|
| Subject category code |
TJFC |
| Source |
thema |
| 090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN) |
|---|
| Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR) |
TK7868.L6EBK |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Taraate, Vaibbhav. |
| Relator term |
author. |
| Relator code |
aut |
| -- |
http://id.loc.gov/vocabulary/relators/aut |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Digital Logic Design Using Verilog |
| Medium |
[electronic resource] : |
| Remainder of title |
Coding and RTL Synthesis / |
| Statement of responsibility, etc. |
by Vaibbhav Taraate. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
2nd ed. 2022. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
Singapore : |
| Name of producer, publisher, distributor, manufacturer |
Springer Nature Singapore : |
| -- |
Imprint: Springer, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2022. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 online resource |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
online resource |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS |
|---|
| File type |
text file |
| Encoding format |
PDF |
| Source |
rda |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists. . |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic circuits. |
|
|---|
| Topical term or geographic name entry element |
Electronics. |
|
|---|
| Topical term or geographic name entry element |
Logic design. |
|
|---|
| Topical term or geographic name entry element |
Electronic Circuits and Systems. |
|
|---|
| Topical term or geographic name entry element |
Electronics and Microelectronics, Instrumentation. |
|
|---|
| Topical term or geographic name entry element |
Logic Design. |
| 653 #0 - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Logic design -- Data processing |
|
|---|
| Uncontrolled term |
Verilog (Computer hardware description language) |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="https://doi.org/10.1007/978-981-16-3199-3">https://doi.org/10.1007/978-981-16-3199-3</a> |
| Materials specified |
Springer eBooks |
| Public note |
Online access link to the resource |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Library of Congress Classification |
| Koha item type |
E-Book |
