TY  - BOOK
AU  - Taraate,Vaibbhav
ED  - SpringerLink (Online service)
TI  - Digital Logic Design Using Verilog: Coding and RTL Synthesis  
SN  - 9789811631993
AV  - TK7868.L6 
PY  - 2022///
CY  - Singapore
PB  - Springer Nature Singapore, Imprint: Springer
KW  - Electronic circuits
KW  - Electronics
KW  - Logic design
KW  - Electronic Circuits and Systems
KW  - Electronics and Microelectronics, Instrumentation
KW  - Logic Design
KW  - Logic design -- Data processing
KW  - Verilog (Computer hardware description language)
N1  - Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs
N2  - This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.
UR  - https://doi.org/10.1007/978-981-16-3199-3
ER  -