Çok çekirdekli görev-kritik işlemciler için önbellek tasarımı ve gerçeklenmesi / Mert Atamaner ; thesis advisor Oğuz Ergin.

By:

Atamaner, Mert [author]

Contributor(s):

Material type: Text

TextLanguage: Türkçe Publisher: Ankara : TOBB ETÜ Fen Bilimleri Enstitüsü, 2020Description: xiv, 64 pages : illustrations ; 29 cmContent type:

text

Media type:

unmediated

Carrier type:

volume

Other title:

Cache design and implementation for mission-criticalmulticore processors [Parallel title]

Subject(s):

Dissertation note: Tez (Yüksek Lisans Tezi)--TOBB ETÜ Fen Bilimleri Enstitüsü Haziran 2020 Summary: Mutlicore architecutres optimizes the performance and energy overhead by using private and shared caches in the memory hierarchy. Different cores having private caches introduces coherency problem in between different cores. Modern systems employ a coherence protocol scheme into the system to tackle this problem. Two of the most used protocols today are MOESI and MESI protocols. These protocols solve the coherency problem efficiently, however recently it was shown that these protocols can be exploited or used for different purposes. Thesis includes a such a scheme that uses MOESI labels for error correction. Private caches are closely connected to the pipeline and thus requires to be fast. Because of this fact, modern CPUs do not use ECC in private caches(L1). Instead, parity bits are checked for errors and if an error occurs systems crash or are reload to a safe state. Proposed mechanism suggests an alternative for using ECC while being fast enough for pipeline utilizing coherency labels. Shared labeled cache blocks imply that there is at least one other copy of the same data in another L1 cache, and it can be used to reload when a parity bit of such cache blocks imply error. In this thesis, it is shown that it is possible to protect a program during one fourth of its lifetime. Yao et al., reports that coherency protocols can also be exploited to create timing side channels. Since the accesses to shared and exclusive labeled cache blocks takes deterministically distinguishable time, it enables a spy-trojan pair to serially communicate by only measuring the access times to such cache blocks [1]. This communication is made possible by KSM(kernel same page merging) and disabling KSM incurs a significant performance loss. This work proposes a new scheme to prevent communicating through this side channel without the need of disabling KSM. Since the communication depends on back-to-back load operations, it is possible to track and monitor loads to the same cacheblock and introduce noise to the side channel. It is shown that it is possible to disrupt up to %90 of the communication while increasing the runtime %2 to %15.

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Holdings
Item type	Current library	Home library	Collection	Call number	Copy number	Status	Date due	Barcode
Thesis	Merkez Kütüphane Tez Koleksiyonu / Thesis Collection	Merkez Kütüphane	Tezler	TEZ TOBB FBE BİL YL’20 ATA (Browse shelf(Opens below))	1	Ödünç Verilemez-Tez / Not For Loan-Thesis		TZ01126

Tez (Yüksek Lisans Tezi)--TOBB ETÜ Fen Bilimleri Enstitüsü Haziran 2020

Mutlicore architecutres optimizes the performance and energy overhead by using private
and shared caches in the memory hierarchy. Different cores having private caches
introduces coherency problem in between different cores. Modern systems employ a
coherence protocol scheme into the system to tackle this problem. Two of the most used
protocols today are MOESI and MESI protocols. These protocols solve the coherency
problem efficiently, however recently it was shown that these protocols can be exploited
or used for different purposes. Thesis includes a such a scheme that uses MOESI
labels for error correction. Private caches are closely connected to the pipeline and
thus requires to be fast. Because of this fact, modern CPUs do not use ECC in private
caches(L1). Instead, parity bits are checked for errors and if an error occurs systems
crash or are reload to a safe state. Proposed mechanism suggests an alternative for using
ECC while being fast enough for pipeline utilizing coherency labels. Shared labeled
cache blocks imply that there is at least one other copy of the same data in another L1
cache, and it can be used to reload when a parity bit of such cache blocks imply error.
In this thesis, it is shown that it is possible to protect a program during one fourth of its
lifetime.
Yao et al., reports that coherency protocols can also be exploited to create timing
side channels. Since the accesses to shared and exclusive labeled cache blocks takes deterministically distinguishable time, it enables a spy-trojan pair to serially communicate
by only measuring the access times to such cache blocks [1]. This communication
is made possible by KSM(kernel same page merging) and disabling KSM incurs a
significant performance loss. This work proposes a new scheme to prevent communicating
through this side channel without the need of disabling KSM. Since the communication
depends on back-to-back load operations, it is possible to track and monitor loads to the
same cacheblock and introduce noise to the side channel. It is shown that it is possible
to disrupt up to %90 of the communication while increasing the runtime %2 to %15.

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