000			03620nam a2200421 i 4500
999			_c200438858 _d57070
003			TR-AnTOB
005			20230908000950.0
007			ta
008			171111s2018 xxu e mmmm 00| 0 eng d
035			_a(TR-AnTOB)200438858
040			_aTR-AnTOB _beng _erda _cTR-AnTOB
041	0		_atur
099			_aTEZ TOBB FBE BİL YL’20 ATA
100	1		_aAtamaner, Mert _eauthor _9128687
245	1	0	_aÇok çekirdekli görev-kritik işlemciler için önbellek tasarımı ve gerçeklenmesi / _cMert Atamaner ; thesis advisor Oğuz Ergin.
246	1	1	_a Cache design and implementation for mission-criticalmulticore processors
264		1	_aAnkara : _bTOBB ETÜ Fen Bilimleri Enstitüsü, _c2020.
300			_axiv, 64 pages : _billustrations ; _c29 cm
336			_2rdacontent _btxt _atext
337			_2rdamedia _bn _aunmediated
338			_2rdacarrier _bnc _avolume
502			_aTez (Yüksek Lisans Tezi)--TOBB ETÜ Fen Bilimleri Enstitüsü Haziran 2020
520			_aMutlicore architecutres optimizes the performance and energy overhead by using private and shared caches in the memory hierarchy. Different cores having private caches introduces coherency problem in between different cores. Modern systems employ a coherence protocol scheme into the system to tackle this problem. Two of the most used protocols today are MOESI and MESI protocols. These protocols solve the coherency problem efficiently, however recently it was shown that these protocols can be exploited or used for different purposes. Thesis includes a such a scheme that uses MOESI labels for error correction. Private caches are closely connected to the pipeline and thus requires to be fast. Because of this fact, modern CPUs do not use ECC in private caches(L1). Instead, parity bits are checked for errors and if an error occurs systems crash or are reload to a safe state. Proposed mechanism suggests an alternative for using ECC while being fast enough for pipeline utilizing coherency labels. Shared labeled cache blocks imply that there is at least one other copy of the same data in another L1 cache, and it can be used to reload when a parity bit of such cache blocks imply error. In this thesis, it is shown that it is possible to protect a program during one fourth of its lifetime. Yao et al., reports that coherency protocols can also be exploited to create timing side channels. Since the accesses to shared and exclusive labeled cache blocks takes deterministically distinguishable time, it enables a spy-trojan pair to serially communicate by only measuring the access times to such cache blocks [1]. This communication is made possible by KSM(kernel same page merging) and disabling KSM incurs a significant performance loss. This work proposes a new scheme to prevent communicating through this side channel without the need of disabling KSM. Since the communication depends on back-to-back load operations, it is possible to track and monitor loads to the same cacheblock and introduce noise to the side channel. It is shown that it is possible to disrupt up to %90 of the communication while increasing the runtime %2 to %15.
650		7	_aTezler, Akademik _932546
653			_aMulti core processors
653			_aCache
653			_aCoherency protocols
653			_aError tolerance
653			_aError correcting codes
653			_aReliability
653			_aSecurity
653			_aCache Side channels
653			_aGem5
700	1		_aErgin, Oğuz _936153 _eadvisor
710			_aTOBB Ekonomi ve Teknoloji Üniversitesi. _bFen Bilimleri Enstitüsü _977078
942			_2z _cTEZ