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008			060609t20142006enka o 001 0 eng d
020			_a0470020741 _q(electronic bk.)
020			_a9780470020746 _q(electronic bk.)
020			_a9780470020753 _q(electronic bk.)
020			_a047002075X _q(electronic bk.)
020			_z0470020733
020			_z9780470020739
035			_a(OCoLC)70056762 _z(OCoLC)71626104 _z(OCoLC)181842072 _z(OCoLC)441750130 _z(OCoLC)647761278 _z(OCoLC)814396359
037			_aEBL257677 _beBook Library _nhttp://www.eblib.com
040			_aN$T _beng _erda _cN$T _dYDXCP _dOCLCQ _dEBLCP _dMERUC _dE7B _dOCLCQ _dIDEBK _dOCLCQ _dOCLCF _dOCLCQ _dMUX _dNRU _dUKDOC _dDG1 _dDEBSZ _dOCLCO _dOCLCQ _dOCLCO _dDEBBG _dTR-AnTOB
041	0		_aeng
050		4	_aTS156.8 _b.G75 2014EBK
072		7	_aTEC _x009060 _2bisacsh
090			_aTS156.8 _b.G75 2014EBK
100	1		_aGrimble, Michael J. _eauthor _9142233
245	1	0	_aRobust industrial control systems : _boptimal design approach for polynomial systems / _cMichael J. Grimble.
264		1	_aChichester ; _aHoboken, NJ : _bWiley, _c2014.
264		4	_c©2006
300			_a1 online resource (xxii, 676 pages) : _billustrations.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
504			_aBIBINDX
505	0		_aCover Table of Contents List of Acronyms and Symbols Preface 1 Introduction 1.1 MOTIVATION 1.2 SUMMARY OF BOOK 1.3 BOOK ORGANIZATION REFERENCES 2 Frequency Synthesizer for Wireless Applications 2.1 DEFINITION AND CHARACTERISTICS 2.2 PHASE NOISE AND TIMING JITTER 2.3 IMPLEMENTATION OF FREQUENCY SYNTHESIZER 2.4 FREQUENCY SYNTHESIZER FOR WIRELESS TRANSCEIVERS 2.5 OTHER APPLICATIONS OF PLL AND FREQUENCY SYNTHESIZER REFERENCES 3 PLL Frequency Synthesizer 3.1 PLL FREQUENCY SYNTHESIZER BASICS 3.2 FAST-LOCKING TECHNIQUES 3.3 DISCRETE-TIME ANALYSIS AND NONLINEAR MODELING 3.4 DESIGN EXAMPLE: 2.4GHZ INTEGER-N PLL FOR BLUETOOTH REFERENCES 4 EA Fractional-N PLL Synthesizer 4.1 EA FRACTIONAL-N FREQUENCY SYNTHESIZER 4.2 A COMPARATIVE STUDY OF DIGITAL EA MODULATORS 4.3 OTHER APPLICATIONS OF EA-PLL 4.4 MODELING AND SIMULATION OF EA-PLL 4.5 DESIGN EXAMPLE: 900MHz EA-PLL FOR GSM REFERENCES 5 Enhanced Phase Switching Prescaler 5.1 PRESCALER ARCHITECTURE 5.2 ENHANCED PHASE-SWITCHING PRESCALER 5.3 CIRCUIT DESIGN AND SIMULATION RESULTS 5.4 DELAY BUDGET IN THE SWITCHING CONTROL LOOP 5.5 SPURS DUE TO NONIDEAL 45 PHASE SPACING REFERENCES 6 Loop Filter With Capacitance Multiplier 6.1 LOOP FILTER ARCHITECTURE 6.2 LOOP FILTER AND CHARGE-PUMP NOISE MAPPING 6.3 LOOP FILTER WITH CAPACITANCE MULTIPLIER REFERENCES 7 Other Building Blocks of PLL 7.1 VCO 7.2 PHASE-FREQUENCY DETECTOR 7.3 CHARGE-PUMP 7.4 PROGRAMMABLE DIVIDER 7.5 DIGITAL EA MODULATOR 7.6 CHIP LAYOUT REFERENCES 8 Prototype Measurement Results 8.1 PRESCALER MEASUREMENT 8.2 LOOP FILTER MEASUREMENT 8.3 PLL MEASUREMENT REFERENCES 9 Conclusions Appendix.
588	0		_aPrint version record.
650		0	_aProcess control _xAutomation.
650		7	_aTECHNOLOGY & ENGINEERING _xIndustrial Engineering. _2bisacsh
650		7	_aProcess control _xAutomation. _2fast _0(OCoLC)fst01078021
655		7	_aElectronic books. _2local
776	0	8	_iPrint version: _aGrimble, Michael J. _tRobust industrial control systems. _dChichester ; Hoboken, NJ : Wiley, ©2006 _z0470020733 _w(DLC) 2005031937 _w(OCoLC)62290488
856	4	0	_3Wiley Online Library _zOnline access link to the resource _uhttps://doi.org/10.1002/9780470020753
942			_2lcc _cEBK