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020 _a9783030981129
024 7 _a10.1007/978-3-030-98112-9
_2doi
040 _aTR-AnTOB
_beng
_cTR-AnTOB
_erda
041 _aeng
050 4 _aTK7895.E42
072 7 _aTHR
_2bicssc
072 7 _aTEC007000
_2bisacsh
072 7 _aTHR
_2thema
090 _aTK7895.E42EBK
100 1 _aChakravarthi, Veena S.
_eauthor.
_0(orcid)0000-0002-8703-2376
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
245 1 0 _aSoC Physical Design
_h[electronic resource] :
_bA Comprehensive Guide /
_cby Veena S. Chakravarthi, Shivananda R. Koteshwar.
250 _a1st ed. 2022.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2022.
300 _a1 online resource
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- SoC Physical Design Flow and Algorithms -- Physical Design Floor Plan and Placement -- Clock, Reset, and HFN -- Physical Design Routing -- Physical Design Verification.
520 _aSoC Physical Design is a comprehensive practical guide for VLSI designers that thoroughly examines and explains the practical physical design flow of system on chip (SoC). The book covers the rationale behind making design decisions on power, performance, and area (PPA) goals for SoC and explains the required design environment algorithms, design flows, constraints, handoff procedures, and design infrastructure requirements in achieving them. The book reveals challenges likely to be faced at each design process and ways to address them in practical design environments. Advanced topics on 3D ICs, EDA trends, and SOC trends are discussed in later chapters. Coverage also includes advanced physical design techniques followed for deep submicron SOC designs. The book provides aspiring VLSI designers, practicing design engineers, and electrical engineering students with a solid background on the complex physical design requirements of SoCs which are required to contribute effectively in design roles. Provides a comprehensive overview of the skills required for complex SoC design and development; Examines SOC design challenges in nanotechnology scales; Offers readers professional “tricks” to using tools for optimal design runs.
650 0 _aElectrical engineering.
650 0 _aElectronic circuit design.
650 0 _aElectronic circuits.
650 0 _aElectronics.
650 0 _aEmbedded computer systems.
650 1 4 _aElectrical and Electronic Engineering.
650 2 4 _aElectronics Design and Verification.
650 2 4 _aElectronic Circuits and Systems.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
650 2 4 _aEmbedded Systems.
653 0 _aSystems on a chip
700 1 _aKoteshwar, Shivananda R.
_eauthor.
_0(orcid)0000-0003-4299-4069
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
710 2 _aSpringerLink (Online service)
856 4 0 _uhttps://doi.org/10.1007/978-3-030-98112-9
_3Springer eBooks
_zOnline access link to the resource
942 _2lcc
_cEBK