000 01380 a2200361 4500
001 54188
999 _c54188
_d14287
003 TR-AnTOB
005 20200624094423.0
008 061103s2003 enk 00000 eng
020 _a1-4020-7471-9
040 _aETU
041 _aeng
050 _aTK7874.55
_b.V36 2003
090 _aTK7874.55 .V36 2003
100 _aVandenbussche, J.,
_q(Jan)
_929161
245 0 _aSystematic design of analog IP blocks /
_cby J. Vandenbussche, G. Gielen, M. Steyaert.
264 1 _aBoston :
_bKluwer Academic Publishers,
_c2003.
300 _axii,193p.:
_bill.;
_c25cm.
490 0 _aThe Kluwer international series in engineering and computer science ;
_vSECS 738
504 _aIncludes bibliographical references (p. [183]-193).
650 0 _aIntegrated circuit layout
_929164
650 0 _aMetal oxide semiconductors, Complementary
_xDesign and construction
_929166
650 7 _aMetal oksit yarı iletkenleri, Tümleyici
_xTasarım ve yapım
_2etuturkob
_929275
650 _aIntegrated circuits
_923451
650 _aEntegre devreler
_98583
650 _aEntegre devreler
_xÇok büyük ölçekli entegrasyon
_xTasarım ve yapım
_954113
650 _aIntegrated circuits
_xVery large scale integration
_xDesign and construction
_9391
700 _aGielen, Georges
_929162
700 _aSteyaert, Michiel,
_d1959-
_929163
901 _a0017122
902 _aGT
942 _cBK